[Degrees and Academic Honors] [Career Experience] [Volunteer Activities] [Awards] [Engineering Publications]

Rodham E. Tulloss, Ph.D.
Electronic Engineering Curriculum Vitae

Revision: 6 November 2004

P. O. Box 57, Roosevelt, New Jersey 08555-0057, U. S. A.
Phone: +1 609 448 5096
Fax: +1 609 426 4164
Email: ret@njcc.com

Degrees and Academic Honors

  • B.Sc., Mathematics with honors in Philosophy, summa cum laude, Union College, Schenectady, NY, 1966. (Phi Beta Kappa)
  • M.Sc., Mathematics, University of California, Berkeley, 1971.
  • Ph.D., Group in Logic and Methodology of Science, University of California, Berkeley, 1971.

Career Experience

I have done research and published results in three scientific/technical fields: Mathematical Logic (the area of my formal education), Computer Engineering--R&D in Testing of Digital Logic Circuits, and Mycology. My list of engineering publications is attached to this document.

From February, 1996 until the end of 1999, I worked as a consultant in the following areas:

  • architecture and strategy for system level design for testability (in collaboration with client staff, not as trainer of client staff)
  • review and critique of IEEE Std 1149.5 implementations and related documentation
  • technical analysis and support in preparation for, and expert testimony during, test technology related patent litigation
  • assessment of Computer Aided Engineering (CAE) and innovative Data Processing start-ups for venture capitalists
  • preparation of manuals, application notes, marketing/sales presentations, etc. for test technology related devices from major electronics firms--print and hypertext versions
  • assessment of research program development and implementation in electronic testing
  • assistance in development of research grant applications and related technical presentations

After my doctoral studies, I was hired by AT&T Corp. (September, 1971) at their Western Electric (later Bell Laboratories) Engineering Research Center, Hopewell, New Jersey. In March, 1991, I was named a Bell Laboratories Fellow (an honor attained by less than 1% of the research staff of the Labs). I retired from AT&T in January, 1996. My last position was Distinguished Member of Technical Staff.

From 1979 to 1990, I was Supervisor of an R&D group in design, test, and diagnosis of digital electronics. In this field, I was involved both within AT&T and internationally as an expert and received several international awards for excellence. I established three long-lived research teams in three different disciplines and was the major force behind the development of the only laboratory in ERC that was consistently a money-maker despite being a research unit. Among other accomplishments, I established and led what, in its day, was the world-leading research group in Boundary-Scan and Built-In Self-Test.

In 1986 I became the first North American member of an ad hoc, formerly all European, committee to devise a new means of testing electronics in the face of miniaturization beyond the limits of the then existing test technology -- Joint Test Action Group (JTAG). With colleagues from 20 companies, such a method was devised and successfully promulgated as an U.S. and international standard (IEEE Std 1149.1) which has created a revolution in design practice. I have served as co-chair (1 year), vice-chair (1 year) and chair (2 years) of the Working Group that maintains and extends the standard. In 1995, I was elected Chair Emeritus of the Working Group. Since the standard's original publication (1990), I have played a major role in the writing and editing of two major supplements to the standard. In December, 1992, I became editor of another standard that, it was hoped, would provide an important advance in the architecture of test and maintenance in avionics, large computers, and telecommunications systems. This standard (IEEE Std 1149.5) has also been promulgated. In the mid-1990s, avionics test engineers called the document "the Bible of System Testing."

Volunteer Activities

Until very recently, I remained active in engineering societies--primarily the Institute for Electrical and Electronic Engineers (IEEE) and affiliated groups. I served in editorial capacities for a number of engineering technical journals and other publications--most recently IEEE Test Technology Newsletter, IEEE Design and Test of Computers, and Test Points (newsletter of the American Society of Test Engineers (ASTE)). I have been a reviewer and/or organizer for many of the major journals and conferences in my field.

Awards

I received Meritorious and Distinguished Service Awards from the IEEE Computer Society. I was named Test Engineer of 1991 (an international award sponsored by the John Fluke Mfg. Co., Test and Measurement World, and ASTE). In the citation for this award, I am credited with personally inventing or leading the research for every major test technology advance experienced within AT&T manufacturing in the preceding 15 years.

I was elected a Senior Member of the IEEE. I served on the governing board of the ASTE.

In 1995, I received the IEEE Standards Medallion, the highest honor recognizing contribution to electronic standards development and deployment.

In October, 2004, I received the IEEE Test Technology Technical Council Lifetime Achievement Award.

Engineering Publications

  1. (with G. E. Whitney). 1972. The BEST language: a language for use in simulation of digital circuits. Proc. COMPCON72. San Francisco, Sep. 12-14: 211-214.
  2. (with K. To, G. E. Whitney). 1974. Dynamic self-improving system for diagnosis of failing circuits. Proc. 1974 IEEE Int. Symp. Circuits and Systems. San Francisco, April 22-25: 745-749.
  3. (with K. To). 1974. Automatic test systems. IEEE Spectrum 11(9): 44-57.
  4. (with K. To). 1974. The Dictionary Organization and Retrieval Algorithm. Proc. 1974 Semiconductor Test Symp.: Memory & LSI. Cherry Hill, Nov. 5-7: 189-215. [Reprinted: 1994. 25th Anniversary Compendium of Papers from International Test Conference, P. H. Bardell, R. Garcia, K. Parker, and T. W. Williams, eds. (IEEE Computer Society Press, Los Alamitos, California): 177-187.]
  5. (with K. To). 1974. Untangle automatic test equipment. Electronic Design 22(24): 182-186.
  6. (with K. To). 1975. Automatic test systems: problems and benefits. Proc. IEEE Int. Symp. Circuits and Systems. Newton, April 21-23: 348-351.
  7. 1978. Size optimization of fault dictionaries. Proc. 1978 Semiconductor Test Conf. Cherry Hill, Oct. 31- Nov. 2: 264-265.
  8. 1980. Fault dictionary compression: recognizing when a fault may be unambiguously represented by a single failure detection. Proc. 1980 Test Conf. Philadelphia, Nov. 11-13: 368-370.
  9. 1981. Design information flow and test development for new products and ATE requirements. Proc. Electronics Test and Measurement Conf. Chicago, Oct. 5-8: VI-10 - VI-13.
  10. (with R. W. Allen, Jr., C. D. Chen, M. M. Ervin-Willis, K. R. Rahlfs, S. L. Wu). 1981. DORA: A system of CAD post-processors providing test programs and automatic diagnostics data for digital device and board manufacture. Proc. 1981 Int. Test Conf. Philadelphia, October 27-29: 555-560.
  11. (with R. W. Allen, M. M. Ervin-Willis). 1982. DORA: generalized interface between simulation and automatic diagnostics. Proc. 19th Design Automation Conf. Las Vegas, June 14-16: 559-565.
  12. (with R. W. Allen, C. D. Chen, M. M. Ervin-Willis, K. R. Rahlfs, S. L. Wu). 1982. DORA. The Western Electric Engineer Summer: 8-17. [This article won the Best Technical Writing Award from Western Electric Co. in 1982.]
  13. 1983. Automated board testing: coping with complex circuits. IEEE Spectrum 20(7): 38-43.
  14. 1983. ATE of the future--a CAD perspective. IEEE Test Technology Newsletter 4(4): 5-8.
  15. (with M. M. Pradhan, H. Bleeker, F. P. M. Beenker). 1987. Developing a standard for boundary scan implementation. Proc. 1987 Int. Conf. Computer Design. Rye Brook, New York, October 5-8: 462-466.
  16. 1988. (as symposium editor and chair, author of preface) Built-In Self-Test. Proc. National Communications Forum. Chicago, October 3-5: 1787-1804.
  17. (with H. N. Scholz, W. Wach, C. W. Yau). 1988. ASIC implementation of Boundary-Scan and BIST. Proc. 8th Int. Conf. Custom and Semicustom ICs. London, November 1-3: 43.0 - 43.9.
  18. (with C. W. Yau). 1989. BIST & Boundary-Scan for board level test: test program pseudocode. Proc. European Test Conf. Paris, April 12-14: 106-111.
  19. (with C. H. Hao, H. N. Scholz, W. Wach, C. W. Yau). 1989. Computer aided structured design for testability of ASICs. Proc. 8th Australian Conf. Microelectronics. Brisbane, July 12-14: 116-121.
  20. (with C. M. Maunder et al.). 1990. IEEE Standard 1149.1-1990, standard test access port and Boundary-Scan architecture. (IEEE, Piscataway). xi+127 pp.
  21. (as author/editor with C. M. Maunder). 1990. The test access port and boundary-scan architecture. (IEEE Computer Society Press, Los Alamitos). xxii+398 pp.
  22. (with C. W. Yau). 1990. Boundary-Scan for assembled multichip modules. Proc. ISHM'90: 23rd Int. Symp. Microelectronics. Chicago, October 13-17: 364-369.
  23. 1991. Market forces driving acceptance of ANSI/IEEE Std 1149.1-1990 Boundary-Scan. Proc. IEEE Electro '91. New York, April 16-18: 528-533.
  24. (with C. M. Maunder). 1991. Introduction to the Boundary-Scan standard: ANSI/IEEE Std 1149.1-1990. J. Electronic Testing Theory & Application 2: 27-42.
  25. (with C. M. Maunder). 1992. Testability on TAP. IEEE Spectrum 29(2): 34-37.
  26. 1992. System DFT integrates design and test. Test & Measurement World. 12(4): 47.
  27. (with N. Jarwala, D. K. Le, and C. W. Yau). 1992. AT&T Boundary-Scan Master user manual. AT&T Microelectronics, Allentown. iv+81 pp.
  28. (with C. W. Yau, N. Jarwala, et al.). 1992. Boundary-Scan Master evaluation kit. User's guide and command reference. iv+132 pp. + drawings.
  29. 1992. Testing Assembled Multichip Modules Using Boundary-Scan and Built-In Self-Test. in Thin Film Multichip Modules. ed. G. Messner, I. Turlik, J. W. Balde and P. E. Garrou. (International Society for Hybrid Electronics, Reston, Virginia): 545-568
  30. (with C. W. Thatcher). 1993. Towards a test standard for board and system level mixed-signal interconnects. Proc. Int. Test Conf. 1993, Baltimore, October 17-21: 300 -308.
  31. 1993. IEEE 1149 Standards--changing testing, silicon to systems. Proc. Int. Test Conf. 1993. Baltimore, October 17-21: 399-408. [First invited technical paper in history of conference.]
  32. (with C. M. Maunder et al.). 1993. IEEE Standard 1149.1-1990 (includes IEEE Standard 1149.1a-1993) IEEE standard test access port and Boundary-Scan architecture. (IEEE, Piscataway). xvii+154 pp.
  33. 1994. Profiting from boundary-scan. Proc. National Electronic Packaging and Production Conf. West, Anaheim, California, February 27 - March 4: 2380-2388.
  34. (with N. Jarwala et al.). 1994. Boundary-scan testing for electronic subassemblies and systems. AT&T Technical J. 73(2): 40-48.
  35. (with K. Parker et al.). 1995. IEEE Standard 1149.1b-1994, supplement to IEEE Standard 1149.1-1990 (includes IEEE Standard 1149.1a-1993) IEEE standard test access port and Boundary-Scan architecture. (IEEE, Piscataway). 75 pp.
  36. 1995. 1149.5 status. Test Technology Newsletter April [1995]: 4.
  37. 1995. Leaving the wires to last--a functional evaluation model for the IEEE P1149.5 module test and maintenance bus. Proc. Int. Test Conf. 1995, Washington, October 23-25: 797-806.
  38. (with P. McHugh et al.). 1996. IEEE Standard 1149.5-1995 IEEE standard module test and maintenance bus. (IEEE, Piscataway). x+228 pp.
  39. 1998. User manual. Lucent Technologies 497AE and 1215E Boundary-Scan Master 2 Advanced Operational Mode. Lucent Technologies, Microelectronics Group, Allentown. 98 pp.

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